Conventional semiconductor devices generally include a semiconductor substrate, usually a silicon substrate, and a plurality of sequentially formed dielectric interlayers such as silicon dioxide and conductive paths or interconnects made of conductive materials. Copper and copper alloys have recently received considerable attention as interconnect materials because of their superior electromigration and low resistivity characteristics. The interconnects are usually formed by filling copper by a deposition process in features or cavities etched into the dielectric interlayers. The preferred method of copper deposition process is electroplating. In an integrated circuit, multiple levels of interconnect networks laterally extend with respect to the substrate surface. Interconnects formed in sequential interlayers can be electrically connected using vias or contacts.
In a typical interconnect fabrication process; first an insulating dielectric interlayer is formed on the semiconductor substrate. Patterning and etching processes are performed to form features such as trenches and vias in the insulating layer. Then, copper is electroplated to fill all the features. However, the plating process results in a thick copper layer on the substrate some of which needs to be removed before the subsequent step. Conventionally, after the copper plating, CMP process is employed to planarize and then reduce the thickness of this overburden or excess copper layer down to the level of the surface of the barrier or insulation layer. In summary, CMP is used to remove all of the conductors from the surface so that copper-filled features at an interconnect layer are electrically isolated from one another. However, CMP process is a costly and time-consuming process that reduces production efficiency. Furthermore, although CMP can be used with the conventional interlayer dielectrics, it may create problems with low-k dielectrics because of the mechanical force applied on the wafer surface during the CMP process. During the CMP step, ultra low-k or low-k materials may be stressed and may delaminate or other defects may form due to the low mechanical strength of the low-k materials.
Another material removal technique employed for excess copper polishing involves well-known electropolishing processes. In electropolishing, both the material to be removed and a conductive electrode are dipped into the process solution, which may be an electropolishing solution. Typically an anodic (positive) voltage is applied to the material to be removed with respect to the conductive electrode. With the applied voltage, the material is electrochemically dissolved and removed from the wafer surface.
Electropolishing of copper layers has been studied in the literature and the mechanisms of polishing of the film surfaces have been investigated (see for example, R. Vidal and A. West “Copper electropolishing in concentrated phosphoric acid”, J. Electrochemical Society, vol: 142, p:2682, 1995; Shih-Chieh Chang et al. “Micro leveling mechanisms and applications of electropolishing on planarization of copper metallization”, J. Vacuum Science and Technology, B(20), p:2149, 2002). In a typical electropolishing process, the anodic polarization curve looks like the one shown in FIG. 1. As the positive potential applied to the anode (in this example, a substrate such as a wafer with a copper surface film to be electrochemically removed) is increased with respect to an electrode (cathode) placed in the electropolishing solution, the current first increases in a near-linear manner. During this time electrochemical etching starts removing copper from the copper layer. At a potential Von, rate of increase in current gets reduced and the current value saturates at approximately Is. This current saturation region, which is also called limited current density region, is the region when a salt layer, a passivation layer or a boundary layer is formed on the copper surface. This passivation layer has high resistance; it is rich in copper ions and it acts as a diffusion barrier slowing down material removal rate from the surface. As the voltage is further increased beyond the current saturation region, the electropolishing current starts to rise up sharply due to gas-evolution reaction. Electropolishing and smoothing of the surface of the copper layer takes place at or above the current plateau, which is approximately represented by the value Is in our example. It should be noted that the value of voltage and current where the boundary layer forms is a function of various process parameters such as the composition and temperature of the electrolyte, and the amount of stirring or disturbance on the surface of the anode. For example, in commonly used copper electropolishing electrolytes containing phosphoric acid and glycerol, as the acid content is reduced, the value of Is goes down and the value of Von increases. If electropolishing is carried out on a copper coated wafer held by a rotating wafer holder, the value of Is increases as the rotation (rpm) of the wafer increases. Similarly, increased electrolyte temperature causes an increase in the Is value and a decrease in the voltage. The reason for these trends is the fact that higher temperatures and increased agitation at the copper surface decreases the equilibrium thickness of the barrier layer, if all other variables are kept the same.
FIG. 2 illustrates a commonly accepted mechanism for electropolishing a copper film, which is also applicable to electropolishing of many other metals such as stainless steel, Ni, Ta, W etc. In FIG. 2, the exemplary copper layer 20 has a rough surface 21. When this copper layer is placed into an electropolishing solution 22 and a high enough anodic potential (a potential higher than Von in FIG. 1) is applied to it with respect to a counter electrode (not shown) placed in the same solution 22, a passivation layer 23 forms on the surface as explained before. This passivation layer has an effective thickness, which is smaller over protruded regions 24 compared to recessed regions 25 on the surface of the copper layer 20 as shown by arrows in FIG. 2. As a result, higher current density flows to the protruded areas and more material removal takes place in these regions where the thickness of the passivation layer is thinner. This way the surface is flattened and polished.
The simplified description of the mechanism of electropolishing given above is valid under ideal conditions. However, in actuality, the salt layer, or the passivation layer may not be as uniform as shown in FIG. 2. There may actually be defects in the salt layer. These defects may be in the form of discontinuities, voids or thin areas at various locations of the passivation layer. Reasons for such defects may include but are not limited to presence of particulate impurities in the electropolishing solution, presence of bubbles attached to the copper layer surface, and impurities on the copper layer surface that retards formation of a salt layer right above them. A defect in the passivation layer at a specific site on the copper layer surface may result in a reduction of the passivation layer thickness at that location. As described earlier, a thin passivation layer thickness at that specific point then causes more current flow and more copper removal from that site. Such preferential material removal from a specific location on the copper layer surface causes defect formation in the copper layer itself as will be described next with the help of FIGS. 3 to 5E.
FIG. 3 illustrates a semiconductor substrate 100 including a copper film 102 that is being electropolished. The substrate 100 has a dielectric layer 104 having features 108 such as trenches. The features 108 and the top surface of the dielectric layer are coated with a barrier layer 112 and a copper seed layer (not shown) before the deposition of the copper layer 102. The top surface 110 of the dielectric layer will be referred to as field surface hereinafter. As shown in FIG. 3, a passivation layer 114 forms on top surface 116 of the copper layer 102 when electropolishing is initiated. If there is no defect in the passivation layer 114, copper removal can continue until all copper is removed approximately down to the top surface 110. The barrier 112 is then removed either by CMP, reactive ion etching or electropolishing to leave conducting materials only in the features 108. However, any defects formed during the electropolishing process may over-etch copper in certain locations, and if these locations are right above the features 108, copper may be removed from within the features by the time it is removed from the field region. This is not acceptable. Good quality interconnects require features that are completely filled with defect-free copper.
Time-current graph illustrated in FIG. 4A shows a standard current profile applied to the substrate during a typical electropolishing process. This is a current-controlled mode of power application. It is also possible to apply power under voltage controlled mode, i.e. the waveform in FIG. 4A may be voltage rather than current. FIGS. 5A-5E illustrate a portion of the copper plated substrate during the exemplary time periods between t0 through t4, which are also indicated in graph 120 in FIG. 4A. FIGS. 5A-5E illustrate one possible mechanism of formation of a defect in copper layer due to a defect in the passivation layer.
FIG. 5A shows a portion of the copper layer 102 with a top surface 116. The copper layer of this example is to be electropolished and removed all the way to the level of the barrier 112, leaving copper only in the feature 108. FIG. 5A shows the copper layer in the electropolishing solution at time to when the process is first initiated. As shown in FIG. 5B, by the time t1 a passivation layer 114 formed over the copper layer surface. However, unlike the ideal situation depicted in FIG. 2, the passivation layer 114 has a defect 124 in it. The defect 124 renders the passivation layer 114 thinner at that specific location. The dimple or defect 124 in the passivation layer causes more electropolishing current to pass through that location. As shown in FIG. 5C, which depicts the situation at a later time t2, higher current density causes over etching of copper at this location and an over-etched region 122 forms in the top surface of the copper layer 102. This overetching continues as long as the electropolishing current is passed through the copper.
The overetching at the defect location may be accelerated further due to the fact that high current density may cause local heating of the electropolishing solution in the vicinity of the defect, rendering the passivation layer thickness even lower in this location due to increased local temperature. Therefore the over-etched region 122 expands faster into the copper layer 102 towards the barrier layer 112 as can be seen in FIG. 5D, which exemplifies the situation at a time t3. As can be seen from FIG. 5D, the copper in the feature 108 is partially etched by this time, although copper over the field areas have not yet been totally cleared. Once the barrier layer 112 is exposed in area 113, the passivation layer over the barrier layer gets thin or discontinuous as shown in FIG. 5D, because there is no copper ions fed into the passivation layer right above the barrier layer to sustain it. Without the protection of the thick passivation layer 114, as shown in FIG. 5E, electroetching of the copper layer at this location quickly progresses until the exemplary time t4 and forms a large copper loss 126 in the copper layer 102 within the feature 108. Obviously, this is not an acceptable result.
Curve 140 in FIG. 4B also exemplifies formation of a passivation layer, as the current profile 120 shown in FIG. 4A is applied to a substrate having copper layer on it. As shown in FIG. 4B, thickness of the passivation layer increases and may reach a thickness TF and then grow very slowly, if any. During this slow growth regime small changes (such as solution flow, temperature, velocity, defects etc) in process environment can give rise to non-uniformities in the passivation layer as discussed before and as it will be described below. The same graph 140 can also be used to interpret material removal rate during the electropolishing process. In this respect, highest material removal is aftertime to and as the thickness of the passivation layer increases, material removal rate reaches its minimum level at a given applied power.
The example given above discussed one possible way how microscopic defects may form during prior art electropolishing approaches. There are other problems associated with standard electropolishing. For example, during electropolishing, substrates such as wafers are usually moved. This movement is usually in the form of rotation. As can be appreciated, the linear velocity on a rotating substrate such as a wafer is not uniform and it increases from zero at the center to a maximum value at it radius. As discussed previously, the thickness of the salt layer forming on a wafer that is being electropolished, is a function of the amount of stirring or mechanical disturbance at the wafer/solution interface. Higher solution flows or enhanced motion of the wafer surface reduce the thickness of the salt layer and increase removal rate at that location.
Since the linear velocity on a wafer surface is not constant, when a constant waveform such as the one depicted in FIG. 4A is employed, the thickness of the salt layer is expected to grow faster at the center of the rotating wafer compared to the edge due to the lower velocity near the center. This situation can be exemplified in FIG. 6, which illustrates a central portion of a substrate 130 having a copper layer 132 on which a passivation layer 134 is formed. As is seen, thickness of the passivation layer 134 is thickest about the rotation axis AR of the substrate 130 but the thickness of the layer is gradually reduced towards the edge of the substrate. Referring to FIGS. 4A and 6 now, the dotted line 136 shows the thickness profile of the passivation layer at time t1, which is near-flat during this short time period. However, as the time passes, the thickness of the passivation layer grows faster at the center than the edges and the passivation layer 134 with center thick profile is formed by time t4. This thick center gives rise to macroscopic non-uniformity (or within wafer non-uniformity) in the removal rate, removal rate being lower near the center.
Therefore, it is necessary to develop process approaches and systems that can uniformly and repeatably electropolish conductive layers without overetched regions and defects resulting from them.